1. Field of the Invention
This invention relates generally to the field of amplifier circuits, and more particularly to sense amplifier circuits which may be used in conjunction with memory arrays to determine whether the cells in the array are either programmed or erased.
2. Description of the Prior Art
Sense amplifiers in general are utilized to convert a relatively small voltage swing to a higher voltage swing to provide a potential suitable for driving other circuits, which may be, for example, logic circuits.
In the prior art, to determine the programmed or erased state of cells in a memory array typically one sense amplifier is utilized for each column of cells in the array. The condition of cells along a column of the array is determined by connecting the input terminal of the sense amplifier to the column (product term line) and applying an appropriate potential to the word line (row line) which corresponds to the row of cells in which the cell to be read is located. More particularly, if the memory array is comprised of rows and columns of transistors, a typical operation for reading a cell would be to apply a high voltage (approximately 5 volts) to word line which includes the cell to be read. If the cell which is being read is not programmed, approximately two volts will appear on the column which is connected to the input terminal of the sense amplifier. This terminal is typically denoted as PT. If the cell at the intersection of the product term line and word line is programmed, then approximately 1.5 volts will be sensed at the input terminal PT of the sense amplifier. This provides a voltage swing of approximately 0.5 volts. In a typical prior art circuit, such as that illustrated in FIG. 1, a one-half volt swing at input terminal PT results in a voltage swing at the output of between zero and five volts. Another prior art sense amplifier circuit similar to sense amplifier circuit 1 of FIG. 1 herein is disclosed in FIG. 5 of U.S. Pat. No. 4,833,646 to John E. Turner issued May 23, 1989 and assigned to the assignee of this application.
It will be appreciated that since one sense amplifier is used for each column of cells in a memory array, as the array becomes more dense, the increasing number of sense amplifiers required to be utilized can present a current drain problem because it takes DC bias current to detect small voltage changes at S.A. input terminal and amplify it to full voltage swing which may require an undesirably high amount of current for the array.
Turning to FIG. 1, prior art sense amplifier circuit 1 is comprised of a number of stages of N-MOS field effect transistor devices. To illustrate the relationship between sense amplifier circuit 1 and its associated memory cells, the programmed/unprogrammed condition of which is to be determined, memory cells M1-M2, wordlines WL1 and WL2, and product term lines, denoted PTL1 and PTL2 are illustrated in FIG. 1. Input terminal PT is connected to PTL1 and by applying a voltage to WL1, the programmed/unprogrammed state of cell M1 can be determined. Similarly, the programmed/unprogrammed state of cell M2 may be determined by applying a voltage to WL2. Sense amplifier-circuit 1 includes five stages of amplification between input terminal PT, to which a column PTL1 of the memory array is connected for reading the programmed or erased state of a devices connected to. column PTL1, and the final output terminal indicated SA OUT. As mentioned above, one sense amplifier is required for each column and it will of course be appreciated that FIG. 1 illustrates a single sense amplifier which is connected to PTL1 of an associated memory array. In sense amplifier circuit 1, VCC will typically be plus five volts with respect to the ground terminal (indicated by GND) for sense amplifier circuit 1. The first stage of sense amplifier circuit 1 includes N-channel field effect transistor T1 having its drain connected to VCC and its source connected to input terminal PT. It will be recalled that terminal PT is the input terminal and provides the input voltage swing for sense amplifier 1. Transistor T2, also a N-channel field effect transistor, has its drain connected to input terminal PT, its source connected to ground (GND) and its gate connected to input terminal PT. The second stage in sense amplifier circuit includes N-channel field effect transistor T3 having its gate connected to input terminal PT, its source connected to ground and its drain connected to node N1. The second stage of sense amplifier circuit 1 is completed by N-channel depletion mode transistor T4 having its drain connected to VCC, its source connected to node N1 and its gate connected to the gate of N-channel transistor T1, both of which are connected to node N1. The third stage of sense amplifier circuit 1 includes N-channel field effect transistor T5 with its drain connected to VCC, its source connected to node N2 and its gate connected to node N1. N-channel transistor T6 has its drain connected to node N2, its source connected to ground (GND) and its gate connected in common to the gate of N-channel transistor T3 (which is connected to input terminal PT).
In the fourth stage of sense amplifier circuit 1 N-channel depletion mode field effect transistor T7 has its drain connected to VCC, its source connected to node N3 and its gate also connected to node N3. Series connected in this stage to N-channel depletion mode transistor T7 is N-channel field effect transistor T8 which has its drain connected to node N3, its source connected to ground (GND) and its gate connected to node N2. In the fifth and final stage of sense amplifier circuit 1, N-channel depletion mode transistor T9 has its drain connected to VCC, its source connected to node N4 and its gate also connected to node N4. Series connected to N-channel depletion mode field effect transistor T9 is transistor T10 with its drain connected to node N4, its source connected to ground and its gate connected to node N3. Output terminal SA OUT is connected to node N4 by line 3. It will of course be appreciated that the fourth and fifth stages are depletion load inverter stages which provide both signal inversion and amplification.
Although sense amplifier circuit 1 operates satisfactorily, the amount of current required for the circuit operation is from 800 micro-amps to near one milliamp. As the density of related memory arrays increases, the total current required for the sense amplifiers in the array using a sense amplifier of the type illustrated in FIG. 1 becomes undesirably high. The amount of current drawn by sense amplifier circuit 1 may be reduced by adjusting transistor sizes, however with a reduced current flow the speed is correspondingly reduced. Running sense amplifier circuit 1 in the 300 to 400 microamp per column current draw, the speed of operation of sense amplifier circuit 1 is less than that of sense amplifier circuit in accordance with the present invention, which will be described fully hereinafter.
To better appreciate the advantages of the circuit of the present invention, it is helpful to describe the operation of prior art sense amplifier circuit 1 to illustrate its disadvantage in current consumption. When the potential on input terminal PT is low (approximately 1.5 volts in our example), transistors T3 and T6 will be less conductive than transistors T4 and T5, which will result in node Nl being high, node N2 being high and node N3 being low. With node N3 being low, the conduction of transistor T10 will be weak, resulting in node N4 being high, M1, T1, T7, T8, will consume the majority of the currents.
Conversely, when input potential to input terminal PT is high (approximately 2 volts), transistors T3 and T6 will be highly conductive and transistors T4 and T5 weakly conductive. With respect to the potentials at the various nodes, nodes N1 and N2 will be low, which will make node N3 go high and node N4 go low, T3, T4, T5, T6, T9, T10 will take the majority of currents. The additional number of branches in the prior art circuit contribute to additional current comsumption.
Another disadvantage to sense amplifier circuit 1, with respect to the sense amplifier in accordance with the present invention, is that the switching speed of sense amplifier circuit 1 for a desirable sense amplifier current of about 300-400 microamps is slower than that for the sense amplifier circuit of the present invention.